What Spacing Between LVDS Harnesses Running at Different Voltages?

What Spacing Between LVDS Harnesses Running at Different Voltages? image #1

10 Mar 2022

What Spacing Between LVDS Harnesses Running at Different Voltages?


I read your 30/fmax and 3/fmax  theory for cable EM ZONE/ RF reference plane theory (e.g. 30mm for an fmax of 100MHz).

My question: I have one LVDS 600 mV  another LVDS are 300 mV (both superimposed on a 9 VDC reference), so what should be the distance between both harnesses?


Interference between two LVDS links is a very complex issue indeed! You have only provided information on their signal levels, and to be able to predict what we need to do to prevent them interfering with each other we would need to know a great deal more.

However, both LVDS links belong in the same Cable EM Zone as described in my 2001 articles at: www.emcstandards.co.uk/emc-for-systems-and-installations-series, or in my training 2019 course at: www.emcstandards.co.uk/good-enc-engineering-practices-for-electricalel – which is better because it is more up-to-date.

If I had to make a design decision right now, I would improve the shielding of one or both LVDS cables as described in the above two URLs. For example, if an LVDS was unshielded I would use single-braid-shielding; but if it was already single-shielded I would use double-shielding (using double-braid or braid+foil).

It is important to understand that I am talking about double-uninsulated-shielding – with the two overall shield layers in electrical contact with each other along their entire length. Because foil shields are only conductive on one side, in a braid+foil double shield the conductive side of the foil must be in contact with the braid. 

For shielding to work properly and not be a waste of time and money, all of the shields must be terminated in 360 degrees (no pigtails!) to the connector shells at both cable ends. And the mating connectors must maintain 360 degree shielding from those shells right through to the RF References (usually the metal enclosures containing the electronics) at both ends. See the above two URLs for the details.

If the LVDS signals are already shielded, I recommend checking whether the above guidance on shield terminations and connectors has been properly applied, and apply it if not. A great deal of money is wasted worldwide every year on shielding because of bad shield termination techniques. Worse still: a shield that is terminated at one end only, and/or with pigtails instead of a proper 360 degree terminations, can cause more EMC problems at some frequencies than an unshielded cable!

Alternatively – and once again if I had to make a design decision right now  –  to increase confidence that they won’t interfere with each other I would space their cables/bundles apart by at least 12 mm (half an inch) along their entire length whilst fixing them each tight against a metal common-mode (CM) return path that connects the metal enclosures of the electronics at both ends and works well up to the highest frequency it needs to. See the above two URLs for how to determine the highest frequency, and how to construct a suitable CM return path.

BUT I would very much prefer not to have to make an immediate design decision!

I would recommend to my Programme Manager that I need to de-risk this aspect of the project by running a quick little investigation.

I would obtain two identical Bit Error Rate Testers (BERTs) and connect one of the LVDS harnesses to each. With the two harnesses in the preferred final configuration I would run each BERT individually to check that both the 600mV and 300mV LVDSs works well on its own on the worst-case tests – then see if running both BERTs at the same time causes a lower BER on either!

If they do interact in an undesirable manner, then I would apply my preferred solution (either improving shielding or increasing spacing while routed over a CM return path, as described earlier) and repeat the simultaneous BER testing to prove whether it was in fact adequate.

Whenever people, including me, do such investigations/experiments they learn a great deal about the design details that make all the difference. It is very important indeed to learn these details early in a project when changes are quick, easy and low-cost, instead of learning them at the end when even tiny changes cause huge delays and cost a great deal.

Now, I know that Programme Managers are always pressing for projects to be done as fast as possible with the lowest cost. And I also know that Programme Managers usually do not understand that rushing ahead with a design without a clear understanding of what will work, almost always leads to increased delays and costs. So, to stand any chance of meeting the goals of fastest overall project time and lowest overall cost – it is very important to take the time to de-risk critical technical issues early in a project, by doing investigations into them.

Unfortunately, most design engineers have never been taught how to communicate effectively with managers about project planning issues, but my article at https://www.emcstandards.co.uk/getting-what-you-want should help them learn how to describe the benefits of early de-risking in ways that their managers will understand.

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